1. Field of Use
This invention relates to data processing systems and more particularly to memory systems which have a plurality of access ports.
2. Prior Art
While multiprocessing systems are well known, recently it became desirable to implement such systems using single board computers. To facilitate such implementations, single board computers have been designed with onboard random access memories containing two access ports. This enables the onboard computer to access memory directly while other single board computers are able to access the same memory through a common system bus. An article "Multiprocessing System Mixes 8 and 16 Bit Microcomputers" by Joseph P. Barthmaier, published in the February 1980 issue of the publication Computer Design describes one such type of multiprocessor system.
While the above systems provide two points to gaining access to memory, it has been found that the access is carried out in a serial synchronous fashion. That is, a second user can not gain access to memory until the first user has completed its memory operation. This type of system is satisfactory where it is desirable to block out accesses from the system bus or where the data being fetched by the onboard computer is required to continue processing operations. However, in cases where the onboard computer is prefetching data in advance, the operating speed of the overall system is substantially degraded.
Accordingly, it is a primary object of the present invention to provide a system which minimizes the time for accessing memory by a number of competing data processing and handling units.
It is a further object of the present invention to provide a system architecture whose capacity can be easily expanded for accommodating increases in the numbers of data processing and data handling units.